The ability to reduce the physical size of integrated circuits (chips) has led to more combinations of functions on a single chip. Design methodologies have arisen that teach combining pre-existing functional components using standardized bus-based interconnection techniques. These bus-based interconnection techniques are inherently inefficient and unable to scale as system complexity increases.
One limiting factor of bus-based interconnection techniques is bus contention. Bus contention occurs when multiple components attempt to use simultaneously a shared bus. Arbitration protocols determine the allocation of the shared bus. These allocation protocols are performed in real-time on demand. To avoid increasing the latency of access to the bus, the allocation protocols must be kept simple so that rapid computation is facilitated. Many allocation techniques are well known in the art, including: first-come first-served, round-robin, rate monotonic, various weighted prioritization schemes and others.
Another limiting factor of bus-based interconnection techniques is lack of scalability. There are two well-known techniques for scaling bus architectures.
One scaling technique is to increase the performance of a single bus through higher clock rates and increased width. This technique is expensive. The physical realization of a bus in a particular manufacturing process serves to place an upper limit on its clock rate. Additional performance increases require a wider bus, consuming greater amounts of expensive chip area. Furthermore, wide buses are ineffective on small transfers, serving to limit performance increases. An additional burden of this scaling technique is that every component connected to the bus requires redesign.
Another scaling technique is multiple buses. This technique is difficult in practice. A principal difficulty is scheduling transfers across the multiple buses. Similar to the case of a single bus, the scheduling algorithm must be simple in order to facilitate its computation to avoid introducing delay. The required simplicity of the algorithm reduces its effectiveness.
Another limiting factor in bus-based methodologies is the lack of a unified scheduling capability. The existing methodologies lack a coherent mechanism for an individual component to adapt its communication requirements to the capabilities of the system in which it is placed. System designers are forced to create ad-hoc mechanisms to regulate the communication demands of individual components and to integrate them into the overall system.
A communications technique is required that is efficient and scales well as system complexity increases.